Messages in this thread | | | From | David Mosberger <> | Date | Fri, 2 Aug 2002 09:53:46 -0700 | Subject | Re: adjust prefetch in free_one_pgd() |
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>>>>> On 02 Aug 2002 18:58:53 +0100, Alan Cox <alan@lxorguk.ukuu.org.uk> said:
>> Cacheable and side-effects don't go together. Even without >> explicit software prefetches, most modern CPUs will happily and >> aggressively prefetch stuff from cacheable translations.
Alan> Yes we got burned on that with the latest AMD processors. They Alan> prefetch into an area we accidentally have marked with Alan> differing cachabilities between kernel and user space when Alan> using the nv binary driver stuff (but its our bug not Alan> theirs). There's a horrid hack in 2.4.19rc to deal with it Alan> pending merging the proper patches
Yes, I'm well aware of this issue as ia64 has basically the same setup in this regard. For ia64, it seems to be acceptable to require that AGP DMA operates in coherent mode, so that all the memory can be mapped cacheable. With old chipsets, coherent AGP DMA is slow, but with more recent chipsets (including hp's zx1), there won't be a performance penalty. I realize that this isn't a solution for x86 as there is too much of an installed base.
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