Messages in this thread | | | Date | Sat, 08 Jun 2002 17:53:25 -0700 (PDT) | Subject | Re: PCI DMA to small buffers on cache-incoherent arch | From | "David S. Miller" <> |
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From: Roland Dreier <roland@topspin.com> Date: 08 Jun 2002 17:40:24 -0700
Or should we leave that usage unless it is observed causing problems (since we almost always get lucky and don't touch the rest of the cache line near the DMA)?
I think passing in a 4 byte chunk and assuming the rest of the cacheline is unmodified is a valid expectation the more I think about it.
This means what MIPS is doing is wrong. For partial cacheline bits it can't do the invalidate thing. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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