Messages in this thread | | | From | Paul Mackerras <> | Date | Tue, 19 Mar 2002 10:52:40 +1100 (EST) | Subject | Re: 7.52 second kernel compile |
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Linus Torvalds writes:
> Oh, you're cycle timer is too slow to be interesting, apparently ;(
The G4 has 4 performance monitor counters that you can set up to measure things like ITLB misses, DTLB misses, cycles spent doing tablewalks for ITLB misses and DTLB misses, etc. I hacked up a measurement of the misses and total cycles doing tablewalks during a kernel compile and got an average of 36 cycles per DTLB miss and 40 cycles per ITLB miss on a 500MHz G4 machine. What I need to do now is to put some better infrastructure for using those counters in place and try your program using those counters instead of the timebase.
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