Messages in this thread | | | Date | Mon, 23 Dec 2002 04:46:05 -0500 (EST) | From | Zwane Mwaikambo <> | Subject | RE: [PATCH][2.4] generic cluster APIC support for systems with m ore than 8 CPUs |
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On Sun, 22 Dec 2002, Martin J. Bligh wrote:
> > May be we can add some generic NUMA awareness in it. But I am not fully aware of the way interrupt routing happens in various NUMA systems. If I can get this information I can look into, how can we have the generic NUMA support in the new IRQ distribution code. > > Mmm... well it's late and I'm tired, but off the top of my head ... you > need to map from each PCI bus to the closest set of cpus - for me that's > a simple bus_to_node mapping (not sure that bit is added to the topology > infrastructure yet, but it's a trivial patch that's floating around ... > I'll try to dig out out and add it to the 2.5-mjb tree). Then just limit > the distrubtion for an interrupt to the closest set of CPUs (for UMA SMP > would just be cpu_online_map), and have another abstracted function that > sets IO-APIC distribution up to a certain CPU (if doing balancing explicity) > or group thereof. But it's late, so if that makes no sense, I'll take it > all back in the morning ;-)
How about using logical destination mode when programming the IOAPIC? Currently we do physical in io_apic.c (the reason why it breaks on NUMAQ) This way we can get node affinity just by setting the Destination Field for an IOREDTBL to APIC_BROADCAST_ID and also targetting single cpus on a node becomes node generic.
Cheers, Zwane Mwaikambo
PS This suggestion also comes with a possible nonsense disclaimer as i'm also about to go to bed ;)
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