Messages in this thread | | | Date | Thu, 3 Jan 2002 15:57:34 +0100 (MET) | From | "Maciej W. Rozycki" <> | Subject | Re: [PATCH] 2.4.17/2.5.1 apic.c LVTERR fixes |
| |
On Sun, 23 Dec 2001, Mikael Pettersson wrote:
> The Intel P6 local APIC internally signals an Illegal Vector error > whenever a zero vector is written to an LVT entry, even if the entry > is simultaneously masked. The bug is that apic.c triggers these errors > when the contents of LVTERR is defined by the BIOS and not the kernel, > which can cause unexpected interrupts on unknown vectors. This typically > happens at boot-time initialisation, PM suspend, and PM resume. > > The patch eliminates the problem by changing the initialisation order > in apic.c's clear_local_APIC() and apic_pm_resume() to ensure that LVTERR > is masked when we write (potentially) null vectors to LVT entries. [...] > @@ -84,6 +88,8 @@ > apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); > if (maxlvt >= 4) > apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); > + apic_write(APIC_ESR, 0); > + v = apic_read(APIC_ESR); > }
You mustn't access the ESR unconditionally -- it doesn't exist in the i82489DX. Also check the Pentium erratum 3AP for possible issues (I can't recall if writing is safe -- possibly only the contents are lost).
Also note that's really an APIC and not a kernel bug -- writing a previously read value to a register is defined as valid by Intel.
-- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |