Messages in this thread | | | Date | Mon, 14 Jan 2002 17:24:54 +1100 | From | Anton Blanchard <> | Subject | Re: memory-mapped i/o barrier |
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Hi,
> Here's a copy of a patch I just got accepted into the 2.5 patch for > ia64, and I'm wondering if you guys will accept something similar. On > mips64, mmiob() could just be implemented as a 'sync', but I'm not > sure how to do it (or if it's even necessary) on other platforms. > Please let me know what you think. I wrote a small documentation file > for the macro that appears at the top of the patch. > > Thanks, > Jesse > > > diff -Naur --exclude=*~ --exclude=TAGS linux-2.4.17-ia64/Documentation/mmio_barrier.txt linux-2.4.17-ia64-mmiob/Documentation/mmio_barrier.txt > --- linux-2.4.17-ia64/Documentation/mmio_barrier.txt Wed Dec 31 16:00:00 1969 > +++ linux-2.4.17-ia64-mmiob/Documentation/mmio_barrier.txt Tue Jan 8 15:57:37 2002 > @@ -0,0 +1,15 @@ > +On some platforms, so-called memory-mapped I/O is weakly ordered. For > +example, the following might occur: > + > +CPU A writes 0x1 to Device #1 > +CPU B writes 0x2 to Device #1 > +Device #1 sees 0x2 > +Device #1 sees 0x1
Can loads/stores also complete out of order to IO? (the example just shows a store from one cpu passing one from another cpu)
On ppc32/ppc64 this can happen, it is fixed up in the low level pci routines. Is there a case where you cant wrap it up in the low level routines like ppc32/ppc64?
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