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    SubjectRe: Lockups - lost interrupt
    On Thu, 16 Sep 1999 mingo@chiara.csoma.elte.hu wrote:

    > the NMI input of the CPUs is turned off once the local APIC is turned on.
    > So the only input signals to the CPU are LINT0, LINT1 and the APIC bus.
    > LINT1 is historically the NMI signal of the motherboard, broadcasted to
    > all CPUs. We knew this pretty well. I'm right now experimenting with

    Not necessarily -- per MPS, NMI needs only to be delivered to the BSP.
    Exact LINT0 and LINT1 routing should be described by the MP Configuration
    Table (provided it's correct, sigh).

    > configuring LINT0 as NMI as well, although i feel uneasy about this hack,
    > we do have legitimate cases of through-local-APIC interrupts - which would
    > thus become NMIs. It's also horribly dangerous because i have to ack the
    > 8259A IRQ0 interrupt from within the NMI handler - shudders. And it

    No, no, no. Although MPS does not explicitly forbide ceasing to connect
    of any IRQ lines to I/O APICs, in real life the only IRQs that may be
    unconnected are IRQ0 and IRQ13 due to legacy EISA chipsets. As we do not
    care of EISA DMA chaining interrupts (do we?), we may set up IRQ0 as a
    "through-8259A" interrupt which is more reliable and it needs no acking at
    all. This is the Intel-recommended way of handling DMA chaining
    interrupts, BTW -- see the 82489DX datasheet. In short, after merging in
    my patches, no board should ever use ExtINTA interrupts when in the
    symmetric mode.

    In fact there is no difference between configuring LINT0 as Fixed and NMI
    -- none of them make INTA cycles reach 8259As.

    Of course, there might exist a board that would need ExtINTA interrupts
    but it's pretty unlikely and even if it existed it would be an ancient
    proprietary design and it really would not be able to receive periodic
    NMIs in a standard manner. I doubt such boards exist. If you know of
    such one, let me know.

    > violates the MP standard. I've tried some other hacks as well, and there

    AFAIK, the MPS does not force any specific requirements on delivery modes
    in the symmetric mode -- it does specify the routing of IRQ lines and the
    AT compatibility. If you know of a specific paragraph of MPS that stands
    in contradiction to my proposals, please name it!

    > is yet another trick to be tried: we can also set up the local APIC's
    > performance counter LVT into NMI mode, and switch on the performance
    > counter that counts timer cycles ... then we'll get periodic NMIs. I'm
    > pretty much dedicated now to get the NMI oopser done without impacting
    > IRQ0 distribution.

    How would you perform this? The PC does not provide a configurable
    delivery mode -- it's always "Fixed". And even if it would it's
    completely unportable -- it does not exist on i486 and Pentium systems at
    all.

    > dont bother, i've already put the NMI oopser into my APIC tree (and
    > modified it), and hacked away on it. Please for now just send your timer
    > and 486 fixes and i'll merge them in - after that we can still look for
    > better ways of doing NMI-broadcasts.

    Tomorrow, as I wrote. The oopser is not an absolute necessity -- it may
    as well go into 2.5 -- I'd just like to look at it while I am at i386/SMP.

    --
    + Maciej W. Rozycki, Technical University of Gdansk, Poland +
    +--------------------------------------------------------------+
    + e-mail: macro@ds2.pg.gda.pl, PGP key available +


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