Messages in this thread | | | Date | Sun, 6 Jun 1999 19:21:35 +0300 | From | Matti Aarnio <> | Subject | Re: EPIC |
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On Sun, Jun 06, 1999 at 09:08:28AM -0700, David S. Miller wrote: > You have precluded the possibility of dispatching multiple bundles per > clock cycle, and I am rather sure this will be a characteristic of > various EPIC processors. ...
You are right, but lets see; presumed 1 clock per bundle (or multiple bundles) means the instruction stream must be at least 16 bytes wide, and if two bundles at the time are to be executed, 32 byte memory read width is needed. Gee, that is quite a monster..
Of course having wide cache-cpu bus does not mandate as wide main-memory interface.
Definitely not cheap systems.
> Later, > David S. Miller > davem@redhat.com
/Matti Aarnio <matti.aarnio@sonera.fi>
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