Messages in this thread | | | Subject | Re: Thread-private mappings and graphics (was Re: Per-Processor Data Page) | From | David Wragg <> | Date | 21 Dec 1999 01:16:06 +0000 |
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Richard Henderson <rth@twiddle.net> writes: > On Thu, Dec 16, 1999 at 04:40:09PM -0800, Linus Torvalds wrote: > > (The early alpha implementation of LD_L + ST_C was entierly uncached, and > > just took a hundred cycles or more to generate a SMP-safe lock. Ugh. > > Double-ugh. Intel does it in 20 cycles or so, and I think even that is > > excessive, but they probably have good synchronization reasons for it). > > FWIW, I measure ev56 and ev67 taking ~40 ticks for a ll/sc pair. > It's just ev4 that takes over 300, and there are vanishingly few > smp ev4s still running.
Yes, but you will typically also need a memory barrier instruction, won't you? I have seen figures (from a DEC/Compaq guy) for the cost of an uncontended mutex lock+unlock over the Alpha generations, and it looked to have stayed pretty constant relative to the typical IPC for the processors. I suppose that as ll/sc has got cheaper, the memory barriers have got more expensive.
David Wragg
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