Messages in this thread | | | Date | Sun, 24 Jan 1999 11:08:36 +0100 | From | ralf@uni-kobl ... | Subject | Re: Structure vs purism ? |
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On Fri, Jan 22, 1999 at 04:02:20PM -0500, Richard B. Johnson wrote:
> If you get RAM that runs at twice cache-speed you won't need a cache > (there will probably always be an instruction cache so branch prediction > works).
MP systems are getting more and more popular. For them the requirement for caches will continue to exist. Even Cray started to using instruction caches for the SV vectors; good 'ole Seymour would probably commit suicide if he'd know that ;-) Large efforts in CPU and bus systems over the last years has gone into technique which allows to tolerate latencies. The R10000 is one example; probably the most interesting ideas are being used in Tera's proprietary architecture of a multithreaded CPU. The actual hope is that these techniques combined with faster RAM technologies of the future will provide a short enough latency to allow CPUs to keep busy most of the time.
Ralf
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