Messages in this thread | | | Date | Mon, 18 Jan 1999 08:51:05 +1100 | From | Richard Gooch <> | Subject | Re: MSR/performance monitoring for PPro |
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David Wragg writes: > Richard Gooch <rgooch@atnf.csiro.au> writes: > > Hi, all. While trying to track down the source of variability in a > > memory-intensive task (running on a PPro), I've been trying to gain > > access to the CPU performance monitoring facilities. I've trawled the > > Intel developer's WWW site and all I can come up with is a document > > for the Pentium and Pentium/MMX which discusses this. There I see that > > MSR# 0x11 is the "Control and Event Select Register". However, any > > attempts to read or write this register result in a general protection > > fault. > > [snip] > > So it looks like I need a list of MSRs specifically for the Pentium > > Pro. Does anybody have such a list, or a URL I can use? > > The "Pentium Pro Family Developer's Manual Volume 3: Operating System > Writer's Guide" (document number 242692) has an appendix on the > performance monitoring counters, and a full list of MSRs (well, except > for the ones they kept secret). On the Intel website they seem to have > superceded this with an equivalent document for the whole P6 range, > but that probably has the same information. If not, mail me for the > old one.
Yes, since I sent that message I speculatively downloaded V3 (24319201.pdf), and upon reading it found info on both the P5 and P6 performance MSRs. Chapter 14 talks about debugging and performance monitoring, Appendix A lists the perfmon events and Appendix B lists the MSRs.
> I don't see MSR 0x11 in the list.
It's a P5 thing. For the P6 you use 0x186 and 0x187 for counter 0 and counter 1, respectively.
Since I have your attention, I'd like to ask another question. Looking at table A1 I see event# 0x85 (ITLB_MISS), which appears to be instruction TLB misses. There doesn't seem to be a data TLB miss event. Am I misinterpreting the 'I' in "ITLB", or does the event I want not exist?
Regards,
Richard....
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