Messages in this thread | | | Date | Fri, 9 May 1997 18:46:06 +0200 | From | Martin Mares <> | Subject | Re: [PATCH] NMI trap revised (was Re: NMI errors in 2.0.30??) |
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Hi,
> If bit 2 and 3 are not set (0), NMI checks are enabled so bit 6 and 7 are > valid. If bit 2 and 3 are set (1), we cannot receive an NMI caused by > memory parity or I/O CH CHK. When not set, you receive no NMI only if bit > 7 of 0x70 is set (NMI interrupts disabled), and that bits are still valid.
We probably can receive a memory error NMI if we run on a board with ECC RAM even if the parity checks are disabled. I'll look at the ECC specs in various chipsets tonight and think of incorporating such thing to my generic chipset support (now under development).
Martin
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