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SubjectRe: pentiums extended register set?
Hello!

>>>>> "Marty" == "Marty Leisner" <leisner@sdsp.mc.xerox.com> writes:
Marty> Is there any means to get to the pentiums extended register
Marty> set?

I guess you mean the MSRs (``Machine Status Registers''). These
registers should not be readable by Ring 3 programs, because reading
the wrong register may cause the machine to hang. Nevertheless, the
following pieces of C code can be used to read from and write to an
MSR at CPL0: (this code is untested, use them at your own risk)

extern __inline__ unsigned long long int rdmsr(unsigned long reg)
{
unsigned long long int x;
__asm__ volatile (".byte 0x0f, 0x32"
: "=A" (x)
: "c" (reg));
return x;
}

extern __inline__ void wrmsr(unsigned long reg, unsigned long long int value)
{
__asm__ volatile (".byte 0x0f, 0x30"
: : "c" (reg), "A" (value));
}


Marty> Specifically, I understand there's a register which counts
Marty> clock cycles since reset....

The following short piece of C code reads this register, the TSC
("Time Stamp Counter") (even in Ring 3):

extern __inline__ unsigned long long int rdtsc()
{
unsigned long long int x;
__asm__ volatile (".byte 0x0f, 0x31" : "=A" (x));
return x;
}

Marty> Most of the registers have to read in CPL0 -- so I assume
Marty> its relatively simple to add ioctl's to some type of
Marty> module... or add them to /proc...

The only MSRs which are interesting for Ring 3 programs are the
performance monitoring MSRs. But an ioctl() call (or a /proc file
system access) adds a lot of overhead to MSR access. Even the system
call overhead might be too much. I guess the only solution is to
create a call gate from Ring 3 to Ring 0, but I don't know how do such
things yet.

BTW: Why doesn't Linux use such call gates to implement system calls?

cu
Florian


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