Messages in this thread | | | Date | Thu, 9 May 2024 14:38:56 -0700 | Subject | Re: [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling | From | Florian Fainelli <> |
| |
On 5/9/24 13:47, Christian Marangi wrote: > Rework the handling of the CBR address and cache it. This address > doesn't change and can be cached instead of reading the register every > time. > > This is in preparation of permitting to tweak the CBR address in DT with > broken SoC or bootloader. > > bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with > legacy brcm47xx/brcm63xx and generic BMIPS target. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> -- Florian
[unhandled content-type:application/pkcs7-signature] | |