Messages in this thread | | | Date | Thu, 9 May 2024 09:01:56 -0700 | Subject | Re: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property | From | Florian Fainelli <> |
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On 5/8/24 10:17, Christian Marangi wrote: > On Wed, May 08, 2024 at 06:14:34PM +0100, Conor Dooley wrote: >> On Wed, May 08, 2024 at 07:07:18PM +0200, Christian Marangi wrote: >>> Document brcm,bmips-cbr-reg property. >>> >>> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0 >>> if called from TP1. The CBR address is always the same on the SoC >>> hence it can be provided in DT to handle broken case where bootloader >>> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1. >>> >>> Usage of this property is to give an address also in these broken >>> configuration/bootloader. >>> >>> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> >>> --- >>> .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++ >>> 1 file changed, 23 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml >>> index 975945ca2888..77f73ab48c11 100644 >>> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml >>> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml >>> @@ -55,6 +55,15 @@ properties: >>> under the "cpus" node. >>> $ref: /schemas/types.yaml#/definitions/uint32 >>> >>> + brcm,bmips-cbr-reg: >>> + description: Reference address of the CBR. >> >> Pretty sure that Rob commented last time that there's no definition >> anywhere here of CBR, but I don't see either a response to him or an >> explanation in v3 as to what CBR means. >> > > Sorry I missed it.
FWIW, CBR mean Core Base Register. It is accessed via co-processor 0, register 22, selector 6 using the MIPS processor's way of adding custom co-processor registers. -- Florian
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