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SubjectRe: [PATCH v12 6/6] PCI: qcom: Add OPP support to scale performance
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On 4/30/2024 10:56 AM, Manivannan Sadhasivam wrote:
> On Sat, Apr 27, 2024 at 07:22:39AM +0530, Krishna chaitanya chundru wrote:
>> QCOM Resource Power Manager-hardened (RPMh) is a hardware block which
>> maintains hardware state of a regulator by performing max aggregation of
>> the requests made by all of the clients.
>>
>> PCIe controller can operate on different RPMh performance state of power
>> domain based on the speed of the link. And this performance state varies
>> from target to target, like some controllers support GEN3 in NOM (Nominal)
>> voltage corner, while some other supports GEN3 in low SVS (static voltage
>> scaling).
>>
>> The SoC can be more power efficient if we scale the performance state
>> based on the aggregate PCIe link bandwidth.
>>
>> Add Operating Performance Points (OPP) support to vote for RPMh state based
>> on the aggregate link bandwidth.
>>
>> OPP can handle ICC bw voting also, so move ICC bw voting through OPP
>> framework if OPP entries are present.
>>
>> As we are moving ICC voting as part of OPP, don't initialize ICC if OPP
>> is supported.
>>
>> Before PCIe link is initialized vote for highest OPP in the OPP table,
>> so that we are voting for maximum voltage corner for the link to come up
>> in maximum supported speed.
>>
>> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++++------
>> 1 file changed, 67 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 465d63b4be1c..40c875c518d8 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>
> [...]
>
>> @@ -1661,6 +1711,9 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
>> ret = icc_disable(pcie->icc_cpu);
>> if (ret)
>> dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret);
>> +
>> + if (!pcie->icc_mem)
>> + dev_pm_opp_set_opp(pcie->pci->dev, NULL);
>
> At the start of the suspend, there is a call to icc_set_bw() for PCIe-MEM path.
> Don't you want to update it too?
>
> - Mani
>
if opp is supported we just need to call dev_pm_opp_set_opp() only once
which will take care for both PCIe-MEM & CPU-PCIe path.
so we are not adding explicitly there.
- Krishna Chaitanya.


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