Messages in this thread | | | From | Chen-Yu Tsai <> | Date | Thu, 9 May 2024 16:58:19 +0800 | Subject | Re: [PATCH] ASoC: mediatek: mt8192: fix register configuration for tdm |
| |
On Thu, May 9, 2024 at 3:31 PM Hsin-Te Yuan <yuanhsinte@chromium.org> wrote: > > For DSP_A, data is a BCK cycle behind LRCK trigger edge. For DSP_B, this > delay doesn't exist. Fix the delay configuration to match the standard. > > Fixes: 52fcd65414abfc ("ASoC: mediatek: mt8192: support tdm in platform driver") > Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> --- > sound/soc/mediatek/mt8192/mt8192-dai-tdm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c b/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c > index 9ce06821c7d0f..49440db370af0 100644 > --- a/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c > +++ b/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c > @@ -566,10 +566,10 @@ static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream, > tdm_con |= 1 << DELAY_DATA_SFT; > tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT; > } else if (tdm_priv->tdm_out_mode == TDM_OUT_DSP_A) { > - tdm_con |= 0 << DELAY_DATA_SFT; > + tdm_con |= 1 << DELAY_DATA_SFT; > tdm_con |= 0 << LRCK_TDM_WIDTH_SFT; > } else if (tdm_priv->tdm_out_mode == TDM_OUT_DSP_B) { > - tdm_con |= 1 << DELAY_DATA_SFT; > + tdm_con |= 0 << DELAY_DATA_SFT; > tdm_con |= 0 << LRCK_TDM_WIDTH_SFT; > } > > > --- > base-commit: 45db3ab70092637967967bfd8e6144017638563c > change-id: 20240509-8192-tdm-cbf2a73c9dd3 > > Best regards, > -- > Hsin-Te Yuan <yuanhsinte@chromium.org> > >
| |