Messages in this thread | | | Date | Wed, 8 May 2024 17:04:40 +0200 | From | Andrea Parri <> | Subject | Re: [PATCH] riscv/atomic.h: optimize ops with acquire/release ordering |
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> From my understanding of the current version of the RV memory model: > > .aq provides .aq -> all ordering > .rl provides all -> .rl ordering > and because this is RCsc variant of release consistency > .rl -> .aq > > which means > > R/W > amoswap.w.rl > amoswap.w.aq > R/W > > Should act as a full fence? R/W -> rl -> aq -> R/W
Yes, hence the RCsc ("sc" for "sequential consistent") qualification.
> So, I will do the following now: > > 1. Do some benchmarking on real hardware and find out how much overhead > these weak fences add. > 2. Study the LKMM and the RVWMO for the next few weeks/months or however > much time it takes me to confidently reason about things written in > these two models. > 3. Study the locking / related code of RISC-V to see what could break if > we change all these operations in accordance with "Code Porting and > Mapping Guidelines" of RISCV ISA. > 4. I will use the herd7 models of LKMM and RVWMO and see if everything > works as expected after these changes. > > > And If I am convinced after all this, I will send a patch to implement > "Code Porting and Mapping Guidelines" + provide performance numbers from > real hardware. > > Thanks for the detailed explainations and especially regarding how the > LKMM evolved.
Sounds good! Thanks.
Andrea
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