Messages in this thread | | | Date | Fri, 03 May 2024 16:50:02 +0100 | From | Marc Zyngier <> | Subject | Re: [PATCH v2 4/6] KVM: arm64: add emulation for CTR_EL0 register |
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On Wed, 01 May 2024 09:15:09 +0100, Oliver Upton <oliver.upton@linux.dev> wrote: > > On Fri, Apr 26, 2024 at 12:49:48PM +0200, Sebastian Ott wrote: > > CTR_EL0 is currently handled as an invariant register, thus > > guests will be presented with the host value of that register. > > > > Add emulation for CTR_EL0 based on a per VM value. Userspace can > > switch off DIC and IDC bits and reduce DminLine and IminLine sizes. > > > > When CTR_EL0 is changed validate that against CLIDR_EL1 and CCSIDR_EL1 > > to make sure we present the guest with consistent register values. > > Changes that affect the generated cache topology values are allowed if > > they don't clash with previous register writes. > > Sorry I didn't speak up earlier, but I'm not sold on the need to > cross-validate userspace values for the cache type registers. > > KVM should only be concerned about whether or not the selected feature > set matches what hardware is capable of and what KVM can virtualize. So > in the context of the CTR and the cache topology, I feel that they > should be _separately_ evaluated against the host's CTR_EL0. > > Inconsistencies between fields in userspace values should be out of > scope; userspace shares the responsibility of presenting something > architectural, especially if it starts modifying ID registers. Otherwise > I'm quite worried about the amount of glue required to plumb exhaustive > consitency checks for registers, especially considering the lack of > ordering. > > Marc, I know this goes against what you had suggested earlier, is there > something in particular that you think warrants the consistency > checks?
The problem is that we have a dependency chain: individual cache levels are validated against CLIDR/CCSIDR, which are themselves validated against CTR_EL0.
Change one, and everything becomes inconsistent. I absolutely don't trust userspace to do a good job on that, and not validating this will result in extremely hard to debug issues in the guest. Which is why CTR_EL0 was an invariant the first place, and everything derived from it.
Take for example CLIDR_EL1.Lo{UU,UIS,C}. Their values depend on CTR_EL0.{IDC,DIC}. SW is free to check one or the other. If you don't have this dependency, you're in for some serious trouble.
The alternative is to *regenerate* the whole cache hierarchy when CTR_EL0 is written, and too bad if it changes behind the guest's back. Yes, the latter is a problem on its own...
Thanks,
M.
-- Without deviation from the norm, progress is not possible.
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