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    Subject[PATCH v4 42/71] x86/PCI: Switch to new Intel CPU model defines
    Date
    New CPU #defines encode vendor and family as well as model.

    Signed-off-by: Tony Luck <tony.luck@intel.com>
    ---
    arch/x86/pci/intel_mid_pci.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
    index 8edd62206604..933ff795e53e 100644
    --- a/arch/x86/pci/intel_mid_pci.c
    +++ b/arch/x86/pci/intel_mid_pci.c
    @@ -216,7 +216,7 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
    }

    static const struct x86_cpu_id intel_mid_cpu_ids[] = {
    - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
    + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL),
    {}
    };

    @@ -243,7 +243,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
    model = id->model;

    switch (model) {
    - case INTEL_FAM6_ATOM_SILVERMONT_MID:
    + case VFM_MODEL(INTEL_ATOM_SILVERMONT_MID):
    polarity_low = false;

    /* Special treatment for IRQ0 */
    --
    2.44.0

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