Messages in this thread | | | Date | Thu, 11 Apr 2024 14:23:22 -0700 | Subject | Re: [RFC PATCH 18/41] KVM: x86/pmu: Intercept full-width GP counter MSRs by checking with perf capabilities | From | Sean Christopherson <> |
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On Fri, Jan 26, 2024, Xiong Zhang wrote: > From: Mingwei Zhang <mizhang@google.com> > > Intercept full-width GP counter MSRs in passthrough PMU if guest does not > have the capability to write in full-width. In addition, opportunistically > add a warning if non-full-width counter MSRs are also intercepted, in which > case it is a clear mistake. > > Co-developed-by: Xiong Zhang <xiong.y.zhang@intel.com> > Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> > Signed-off-by: Mingwei Zhang <mizhang@google.com> > --- > arch/x86/kvm/vmx/pmu_intel.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index 7f6cabb2c378..49df154fbb5b 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -429,6 +429,13 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > default: > if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || > (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { > + if (is_passthrough_pmu_enabled(vcpu) && > + !(msr & MSR_PMC_FULL_WIDTH_BIT) && > + !msr_info->host_initiated) { > + pr_warn_once("passthrough PMU never intercepts non-full-width PMU counters\n"); > + return 1;
This is broken, KVM must be prepared to handle WRMSR (and RDMSR and RDPMC) that come in through the emulator.
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