Messages in this thread Patch in this message | | | From | Ravi Gunasekaran <> | Subject | [PATCH 2/3] arm64: dts: ti: k3-am68-sk: Add DT node for PCIe | Date | Thu, 21 Sep 2023 15:30:38 +0530 |
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From: Sinthu Raja <sinthu.raja@ti.com>
AM68 Starter kit features with one PCIe M.2 Key M connector interfaced via two SerDes lanes. Update the SerDes configuration for PCIe.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 5df5946687b3..81c2307c77f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -553,3 +553,32 @@ }; }; }; + +&serdes_ln_ctrl { + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>, + <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; +}; + +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; -- 2.17.1
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