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    Subject[PATCH 5.4 048/453] perf/x86/intel: Check PEBS status correctly
    Date
    From: Stephane Eranian <eranian@google.com>

    [ Upstream commit fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27 ]

    The kernel cannot disambiguate when 2+ PEBS counters overflow at the
    same time. This is what the comment for this code suggests. However,
    I see the comparison is done with the unfiltered p->status which is a
    copy of IA32_PERF_GLOBAL_STATUS at the time of the sample. This
    register contains more than the PEBS counter overflow bits. It also
    includes many other bits which could also be set.

    Signed-off-by: Namhyung Kim <namhyung@kernel.org>
    Signed-off-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Link: https://lkml.kernel.org/r/20201126110922.317681-2-namhyung@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/x86/events/intel/ds.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
    index 1aaba2c8a9ba6..eb8bd0eeace7d 100644
    --- a/arch/x86/events/intel/ds.c
    +++ b/arch/x86/events/intel/ds.c
    @@ -1912,7 +1912,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
    * that caused the PEBS record. It's called collision.
    * If collision happened, the record will be dropped.
    */
    - if (p->status != (1ULL << bit)) {
    + if (pebs_status != (1ULL << bit)) {
    for_each_set_bit(i, (unsigned long *)&pebs_status, size)
    error[i]++;
    continue;
    --
    2.27.0


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