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    Subject[PATCH 5.10 690/717] clk: tegra: Do not return 0 on failure
    Date
    From: Nicolin Chen <nicoleotsuka@gmail.com>

    commit 6160aca443148416994c022a35c77daeba948ea6 upstream.

    Return values from read_dt_param() will be either TRUE (1) or
    FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
    or an ERR code on failure.

    So this patch fixes the bug of returning 0 on failure.

    Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
    Cc: <stable@vger.kernel.org>
    Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
    Signed-off-by: Thierry Reding <treding@nvidia.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/clk/tegra/clk-dfll.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    --- a/drivers/clk/tegra/clk-dfll.c
    +++ b/drivers/clk/tegra/clk-dfll.c
    @@ -1856,13 +1856,13 @@ static int dfll_fetch_pwm_params(struct
    &td->reg_init_uV);
    if (!ret) {
    dev_err(td->dev, "couldn't get initialized voltage\n");
    - return ret;
    + return -EINVAL;
    }

    ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
    if (!ret) {
    dev_err(td->dev, "couldn't get PWM period\n");
    - return ret;
    + return -EINVAL;
    }
    td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);


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