Messages in this thread | | | Date | Wed, 2 Dec 2020 19:10:08 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86/cpu/amd: Remove dead code for TSEG region remapping |
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On Wed, Dec 02, 2020 at 11:58:15AM -0600, Tom Lendacky wrote: > I believe this is geared towards performance. If the TSEG base address is > not 2MB aligned, then hardware has to break down a 2MB TLB entry if the OS > references the memory within the 2MB page that is before the TSEG base > address. This can occur whenever the 2MB TLB entry is re-installed because > of TLB flushes, etc.
And if this gets reinstated properly, then that explanation belongs over it because nothing else explains what that thing did. So thanks for digging it out.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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