lkml.org 
[lkml]   [2020]   [Dec]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v2 43/48] ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree
    Date
    Add OPP tables and power domains to the Tegra20 device-tree.

    Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
    ---
    .../boot/dts/tegra20-acer-a500-picasso.dts | 4 +
    arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +-
    arch/arm/boot/dts/tegra20-harmony.dts | 6 +-
    arch/arm/boot/dts/tegra20-paz00.dts | 46 +-
    .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 ++++++++++++++++++
    arch/arm/boot/dts/tegra20-seaboard.dts | 6 +-
    arch/arm/boot/dts/tegra20-tamonten.dtsi | 6 +-
    arch/arm/boot/dts/tegra20-trimslice.dts | 12 +
    arch/arm/boot/dts/tegra20-ventana.dts | 6 +-
    arch/arm/boot/dts/tegra20.dtsi | 220 ++++
    10 files changed, 1241 insertions(+), 12 deletions(-)

    diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
    index 40c1bab22155..78b307370a46 100644
    --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
    +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
    @@ -834,6 +834,10 @@ rtc_32k_wifi: clock@1 {
    clock-output-names = "kk3270032";
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    cpus {
    cpu0: cpu@0 {
    cpu-supply = <&vdd_cpu>;
    diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
    index 585a5b441cf6..5ad803fea48f 100644
    --- a/arch/arm/boot/dts/tegra20-colibri.dtsi
    +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
    @@ -495,7 +495,7 @@ reg_3v3_vsys: sys {
    regulator-always-on;
    };

    - sm0 {
    + vdd_core: sm0 {
    regulator-name = "VDD_CORE_1.2V";
    regulator-min-microvolt = <1200000>;
    regulator-max-microvolt = <1200000>;
    @@ -701,6 +701,10 @@ usb-phy@c5004000 {
    vbus-supply = <&reg_lan_v_bus>;
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    clk32k_in: xtal3 {
    compatible = "fixed-clock";
    #clock-cells = <0>;
    diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
    index 86494cb4d5a1..762e12b73e7e 100644
    --- a/arch/arm/boot/dts/tegra20-harmony.dts
    +++ b/arch/arm/boot/dts/tegra20-harmony.dts
    @@ -339,7 +339,7 @@ sys_reg: sys {
    regulator-always-on;
    };

    - sm0 {
    + vdd_core: sm0 {
    regulator-name = "vdd_sm0,vdd_core";
    regulator-min-microvolt = <1200000>;
    regulator-max-microvolt = <1200000>;
    @@ -640,6 +640,10 @@ backlight: backlight {
    default-brightness-level = <6>;
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    clk32k_in: clock@0 {
    compatible = "fixed-clock";
    clock-frequency = <32768>;
    diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
    index 7e49112cd9a1..d30169722282 100644
    --- a/arch/arm/boot/dts/tegra20-paz00.dts
    +++ b/arch/arm/boot/dts/tegra20-paz00.dts
    @@ -26,7 +26,19 @@ memory@0 {
    };

    host1x@50000000 {
    + core-supply = <&core_vdd_reg>;
    +
    + gr2d@54140000 {
    + core-supply = <&core_vdd_reg>;
    + };
    +
    + gr3d@54180000 {
    + core-supply = <&core_vdd_reg>;
    + };
    +
    dc@54200000 {
    + core-supply = <&core_vdd_reg>;
    +
    rgb {
    status = "okay";

    @@ -34,11 +46,16 @@ rgb {
    };
    };

    + dc@54240000 {
    + core-supply = <&core_vdd_reg>;
    + };
    +
    hdmi@54280000 {
    status = "okay";

    vdd-supply = <&hdmi_vdd_reg>;
    pll-supply = <&hdmi_pll_reg>;
    + core-supply = <&core_vdd_reg>;

    nvidia,ddc-i2c-bus = <&hdmi_ddc>;
    nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
    @@ -46,6 +63,10 @@ hdmi@54280000 {
    };
    };

    + vde@6001a000 {
    + core-supply = <&core_vdd_reg>;
    + };
    +
    pinmux@70000014 {
    pinctrl-names = "default";
    pinctrl-0 = <&state_default>;
    @@ -314,6 +335,8 @@ nvec@7000c500 {
    memory-controller@7000f400 {
    nvidia,use-ram-code;

    + core-supply = <&core_vdd_reg>;
    +
    emc-tables@0 {
    nvidia,ram-code = <0x0>;
    #address-cells = <1>;
    @@ -387,10 +410,10 @@ sys_reg: sys {

    core_vdd_reg: sm0 {
    regulator-name = "+1.2vs_sm0,vdd_core";
    - regulator-min-microvolt = <1200000>;
    - regulator-max-microvolt = <1225000>;
    + regulator-min-microvolt = <950000>;
    + regulator-max-microvolt = <1300000>;
    regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
    - regulator-coupled-max-spread = <170000 450000>;
    + regulator-coupled-max-spread = <170000 550000>;
    regulator-always-on;

    nvidia,tegra-core-regulator;
    @@ -401,7 +424,7 @@ cpu_vdd_reg: sm1 {
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <1100000>;
    regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
    - regulator-coupled-max-spread = <450000 450000>;
    + regulator-coupled-max-spread = <550000 550000>;
    regulator-always-on;

    nvidia,tegra-cpu-regulator;
    @@ -425,10 +448,10 @@ ldo1 {

    rtc_vdd_reg: ldo2 {
    regulator-name = "+1.2vs_ldo2,vdd_rtc";
    - regulator-min-microvolt = <1200000>;
    - regulator-max-microvolt = <1225000>;
    + regulator-min-microvolt = <950000>;
    + regulator-max-microvolt = <1300000>;
    regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
    - regulator-coupled-max-spread = <170000 450000>;
    + regulator-coupled-max-spread = <170000 550000>;
    regulator-always-on;

    nvidia,tegra-rtc-regulator;
    @@ -517,6 +540,7 @@ usb@c5000000 {
    compatible = "nvidia,tegra20-udc";
    status = "okay";
    dr_mode = "peripheral";
    + core-supply = <&core_vdd_reg>;
    };

    usb-phy@c5000000 {
    @@ -527,6 +551,7 @@ usb@c5004000 {
    status = "okay";
    nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
    GPIO_ACTIVE_LOW>;
    + core-supply = <&core_vdd_reg>;
    };

    usb-phy@c5004000 {
    @@ -537,6 +562,7 @@ usb-phy@c5004000 {

    usb@c5008000 {
    status = "okay";
    + core-supply = <&core_vdd_reg>;
    };

    usb-phy@c5008000 {
    @@ -549,12 +575,14 @@ mmc@c8000000 {
    wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
    power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
    bus-width = <4>;
    + core-supply = <&core_vdd_reg>;
    };

    mmc@c8000600 {
    status = "okay";
    bus-width = <8>;
    non-removable;
    + core-supply = <&core_vdd_reg>;
    };

    backlight: backlight {
    @@ -569,6 +597,10 @@ backlight: backlight {
    backlight-boot-off;
    };

    + core-domain {
    + power-supply = <&core_vdd_reg>;
    + };
    +
    clk32k_in: clock@0 {
    compatible = "fixed-clock";
    clock-frequency = <32768>;
    diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
    index b84afecea154..7e015cdfbc55 100644
    --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
    +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
    @@ -1,6 +1,46 @@
    // SPDX-License-Identifier: GPL-2.0

    / {
    + core_opp_table: core-power-domain-opp-table {
    + compatible = "operating-points-v2";
    + opp-shared;
    +
    + core_opp_950: opp@950000 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-level = <950000>;
    + };
    +
    + core_opp_1000: opp@1000000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-level = <1000000>;
    + };
    +
    + core_opp_1100: opp@1100000 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-level = <1100000>;
    + };
    +
    + core_opp_1200: opp@1200000 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-level = <1200000>;
    + };
    +
    + core_opp_1225: opp@1225000 {
    + opp-microvolt = <1225000 1225000 1300000>;
    + opp-level = <1225000>;
    + };
    +
    + core_opp_1275: opp@1275000 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-level = <1275000>;
    + };
    +
    + core_opp_1300: opp@1300000 {
    + opp-microvolt = <1300000 1300000 1300000>;
    + opp-level = <1300000>;
    + };
    + };
    +
    emc_icc_dvfs_opp_table: emc-dvfs-opp-table {
    compatible = "operating-points-v2";

    @@ -8,102 +48,1003 @@ opp@36000000 {
    opp-microvolt = <950000 950000 1300000>;
    opp-hz = /bits/ 64 <36000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    };

    opp@47500000 {
    opp-microvolt = <950000 950000 1300000>;
    opp-hz = /bits/ 64 <47500000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    };

    opp@50000000 {
    opp-microvolt = <950000 950000 1300000>;
    opp-hz = /bits/ 64 <50000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    };

    opp@54000000 {
    opp-microvolt = <950000 950000 1300000>;
    opp-hz = /bits/ 64 <54000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    };

    opp@57000000 {
    opp-microvolt = <950000 950000 1300000>;
    opp-hz = /bits/ 64 <57000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    };

    opp@100000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <100000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@108000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <108000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@126666000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <126666000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@150000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <150000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@190000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <190000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@216000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <216000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@300000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <300000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@333000000 {
    opp-microvolt = <1000000 1000000 1300000>;
    opp-hz = /bits/ 64 <333000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    };

    opp@380000000 {
    opp-microvolt = <1100000 1100000 1300000>;
    opp-hz = /bits/ 64 <380000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    };

    opp@600000000 {
    opp-microvolt = <1200000 1200000 1300000>;
    opp-hz = /bits/ 64 <600000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    };

    opp@666000000 {
    opp-microvolt = <1200000 1200000 1300000>;
    opp-hz = /bits/ 64 <666000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    };

    opp@760000000 {
    opp-microvolt = <1300000 1300000 1300000>;
    opp-hz = /bits/ 64 <760000000>;
    opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1300>;
    + };
    + };
    +
    + gr2d_dvfs_opp_table: gr2d-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@133000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <133000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@171000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <171000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@247000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <247000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@300000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + gr3d_dvfs_opp_table: gr3d-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@114000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <114000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@161500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <161500000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@161500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <161500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@209000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <209000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@218500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <218500000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@247000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <247000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@247000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <247000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@256500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <256500000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@285000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <285000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@285000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <285000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@304000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <304000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@323000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <323000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@333500000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <333500000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@333500000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <333500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@351500000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <351500000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@361000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <361000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@380000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <380000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@400000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <400000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@400000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <400000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + disp1_dvfs_opp_table: disp1-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@158000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <158000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@190000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <190000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + disp2_dvfs_opp_table: disp2-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@158000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <158000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@190000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <190000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + dsi_dvfs_opp_table: dsi-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@100000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <100000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@500000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <500000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + epp_dvfs_opp_table: epp-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@133000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <133000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@171000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <171000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@247000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <247000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@300000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + hdmi_dvfs_opp_table: hdmi-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@148500000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <148500000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + host1x_dvfs_opp_table: host1x-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@104500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <104500000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@133000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <133000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@166000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <166000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + ide_dvfs_opp_table: ide-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@100000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <100000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + mipi_dvfs_opp_table: mipi-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@40000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <40000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@60000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <60000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1275>;
    + };
    + };
    +
    + mpe_dvfs_opp_table: mpe-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@104500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <104500000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@142500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <142500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@152000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <152000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@190000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <190000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@190000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <190000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@228000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <228000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@228000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <228000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@237500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <237500000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@266000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <266000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@275500000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <275500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@300000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x0003>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@300000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x000C>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + ndflash_dvfs_opp_table: ndflash-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@130000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <130000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@150000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <150000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@158000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <158000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@164000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <164000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + nor_dvfs_opp_table: nor-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@92000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <92000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    + };
    +
    + pcie_dvfs_opp_table: pcie-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@250000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <250000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + sdmmc1_dvfs_opp_table: sdmmc1-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@44000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <44000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@52000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <52000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    + };
    +
    + sdmmc2_dvfs_opp_table: sdmmc2-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@44000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <44000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@52000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <52000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    + };
    +
    + sdmmc3_dvfs_opp_table: sdmmc3-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@44000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <44000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@52000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <52000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    + };
    +
    + sdmmc4_dvfs_opp_table: sdmmc4-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@44000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <44000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@52000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <52000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    + };
    +
    + sclk_dvfs_opp_table: sclk-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@95000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <95000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@123500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <123500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@133000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <133000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@152000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <152000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@159500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <159500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@171000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <171000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@180500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <180500000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@190000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <190000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@207000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <207000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@218500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <218500000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@222500000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <222500000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@229500000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <229500000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@240000000,1225 {
    + opp-microvolt = <1225000 1225000 1300000>;
    + opp-hz = /bits/ 64 <240000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1225>;
    + };
    +
    + opp@240000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <240000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@247000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <247000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@256500000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <256500000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@260000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <260000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@262000000,1300 {
    + opp-microvolt = <1300000 1300000 1300000>;
    + opp-hz = /bits/ 64 <262000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1300>;
    + };
    +
    + opp@264000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <264000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@277500000,1300 {
    + opp-microvolt = <1300000 1300000 1300000>;
    + opp-hz = /bits/ 64 <277500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1300>;
    + };
    +
    + opp@285000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <285000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@292500000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <292500000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@300000000,1300 {
    + opp-microvolt = <1300000 1300000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1300>;
    + };
    +
    + opp@300000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1275>;
    + };
    + };
    +
    + tvo_dvfs_opp_table: tvo-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@250000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <250000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1200>;
    + };
    + };
    +
    + usbd_dvfs_opp_table: usbd-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@480000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <480000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + usb2_dvfs_opp_table: usb2-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@480000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <480000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + usb3_dvfs_opp_table: usb3-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@480000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <480000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + vde_dvfs_opp_table: vde-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@95000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <95000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@123500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <123500000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@123500000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <123500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@152000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <152000000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@152000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <152000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@171000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <171000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@209000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <209000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@209000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <209000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@218500000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <218500000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@237500000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <237500000>;
    + opp-supported-hw = <0x0002>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@275500000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <275500000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@285000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <285000000>;
    + opp-supported-hw = <0x0004>;
    + required-opps = <&core_opp_1100>;
    + };
    +
    + opp@300000000,1275 {
    + opp-microvolt = <1275000 1275000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x0001>;
    + required-opps = <&core_opp_1275>;
    + };
    +
    + opp@300000000,1200 {
    + opp-microvolt = <1200000 1200000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x0006>;
    + required-opps = <&core_opp_1200>;
    + };
    +
    + opp@300000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <300000000>;
    + opp-supported-hw = <0x0008>;
    + required-opps = <&core_opp_1100>;
    + };
    + };
    +
    + vi_dvfs_opp_table: vi-opp-table {
    + compatible = "operating-points-v2";
    +
    + opp@85000000,950 {
    + opp-microvolt = <950000 950000 1300000>;
    + opp-hz = /bits/ 64 <85000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_950>;
    + };
    +
    + opp@100000000,1000 {
    + opp-microvolt = <1000000 1000000 1300000>;
    + opp-hz = /bits/ 64 <100000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1000>;
    + };
    +
    + opp@150000000,1100 {
    + opp-microvolt = <1100000 1100000 1300000>;
    + opp-hz = /bits/ 64 <150000000>;
    + opp-supported-hw = <0x000F>;
    + required-opps = <&core_opp_1100>;
    };
    };
    };
    diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
    index c24d4a37613e..b617c69465fc 100644
    --- a/arch/arm/boot/dts/tegra20-seaboard.dts
    +++ b/arch/arm/boot/dts/tegra20-seaboard.dts
    @@ -444,7 +444,7 @@ sys_reg: sys {
    regulator-always-on;
    };

    - sm0 {
    + vdd_core: sm0 {
    regulator-name = "vdd_sm0,vdd_core";
    regulator-min-microvolt = <1300000>;
    regulator-max-microvolt = <1300000>;
    @@ -792,6 +792,10 @@ backlight: backlight {
    default-brightness-level = <6>;
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    clk32k_in: clock@0 {
    compatible = "fixed-clock";
    clock-frequency = <32768>;
    diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
    index 95e6bccdb4f6..bead3c88dec4 100644
    --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
    +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
    @@ -357,7 +357,7 @@ sys_reg: sys {
    regulator-always-on;
    };

    - sm0 {
    + vdd_core: sm0 {
    regulator-name = "vdd_sys_sm0,vdd_core";
    regulator-min-microvolt = <1200000>;
    regulator-max-microvolt = <1200000>;
    @@ -502,6 +502,10 @@ mmc@c8000600 {
    status = "okay";
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    clk32k_in: clock@0 {
    compatible = "fixed-clock";
    clock-frequency = <32768>;
    diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
    index 4bc87bc0c2a4..afcf8ff56087 100644
    --- a/arch/arm/boot/dts/tegra20-trimslice.dts
    +++ b/arch/arm/boot/dts/tegra20-trimslice.dts
    @@ -379,6 +379,10 @@ mmc@c8000600 {
    bus-width = <4>;
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    clk32k_in: clock@0 {
    compatible = "fixed-clock";
    clock-frequency = <32768>;
    @@ -444,6 +448,14 @@ pci_vdd_reg: regulator@4 {
    regulator-always-on;
    };

    + vdd_core: regulator@5 {
    + compatible = "regulator-fixed";
    + regulator-name = "vdd_core";
    + regulator-min-microvolt = <1300000>;
    + regulator-max-microvolt = <1300000>;
    + regulator-always-on;
    + };
    +
    sound {
    compatible = "nvidia,tegra-audio-trimslice";
    nvidia,i2s-controller = <&tegra_i2s1>;
    diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
    index 055334ae3d28..0b03b3b0fd0c 100644
    --- a/arch/arm/boot/dts/tegra20-ventana.dts
    +++ b/arch/arm/boot/dts/tegra20-ventana.dts
    @@ -420,7 +420,7 @@ sys_reg: sys {
    regulator-always-on;
    };

    - sm0 {
    + vdd_core: sm0 {
    regulator-name = "vdd_sm0,vdd_core";
    regulator-min-microvolt = <1200000>;
    regulator-max-microvolt = <1200000>;
    @@ -587,6 +587,10 @@ backlight: backlight {
    default-brightness-level = <6>;
    };

    + core-domain {
    + power-supply = <&vdd_core>;
    + };
    +
    clk32k_in: clock@0 {
    compatible = "fixed-clock";
    clock-frequency = <32768>;
    diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
    index 6ce498178105..39963aa667c6 100644
    --- a/arch/arm/boot/dts/tegra20.dtsi
    +++ b/arch/arm/boot/dts/tegra20.dtsi
    @@ -42,6 +42,8 @@ host1x@50000000 {
    clock-names = "host1x";
    resets = <&tegra_car 28>;
    reset-names = "host1x";
    + operating-points-v2 = <&host1x_dvfs_opp_table>;
    + power-domains = <&pd_core>;

    #address-cells = <1>;
    #size-cells = <1>;
    @@ -55,6 +57,7 @@ mpe@54040000 {
    clocks = <&tegra_car TEGRA20_CLK_MPE>;
    resets = <&tegra_car 60>;
    reset-names = "mpe";
    + power-domains = <&pd_mpe>;
    };

    vi@54080000 {
    @@ -64,6 +67,7 @@ vi@54080000 {
    clocks = <&tegra_car TEGRA20_CLK_VI>;
    resets = <&tegra_car 20>;
    reset-names = "vi";
    + power-domains = <&pd_venc>;
    };

    epp@540c0000 {
    @@ -73,6 +77,7 @@ epp@540c0000 {
    clocks = <&tegra_car TEGRA20_CLK_EPP>;
    resets = <&tegra_car 19>;
    reset-names = "epp";
    + power-domains = <&pd_core>;
    };

    isp@54100000 {
    @@ -82,6 +87,7 @@ isp@54100000 {
    clocks = <&tegra_car TEGRA20_CLK_ISP>;
    resets = <&tegra_car 23>;
    reset-names = "isp";
    + power-domains = <&pd_venc>;
    };

    gr2d@54140000 {
    @@ -91,6 +97,8 @@ gr2d@54140000 {
    clocks = <&tegra_car TEGRA20_CLK_GR2D>;
    resets = <&tegra_car 21>;
    reset-names = "2d";
    + operating-points-v2 = <&gr2d_dvfs_opp_table>;
    + power-domains = <&pd_core>;
    };

    gr3d@54180000 {
    @@ -99,6 +107,8 @@ gr3d@54180000 {
    clocks = <&tegra_car TEGRA20_CLK_GR3D>;
    resets = <&tegra_car 24>;
    reset-names = "3d";
    + operating-points-v2 = <&gr3d_dvfs_opp_table>;
    + power-domains = <&pd_3d>;
    };

    dc@54200000 {
    @@ -110,6 +120,8 @@ dc@54200000 {
    clock-names = "dc", "parent";
    resets = <&tegra_car 27>;
    reset-names = "dc";
    + operating-points-v2 = <&disp1_dvfs_opp_table>;
    + power-domains = <&pd_core>;

    nvidia,head = <0>;

    @@ -138,6 +150,8 @@ dc@54240000 {
    clock-names = "dc", "parent";
    resets = <&tegra_car 26>;
    reset-names = "dc";
    + operating-points-v2 = <&disp2_dvfs_opp_table>;
    + power-domains = <&pd_core>;

    nvidia,head = <1>;

    @@ -242,6 +256,169 @@ tegra_car: clock@60006000 {
    reg = <0x60006000 0x1000>;
    #clock-cells = <1>;
    #reset-cells = <1>;
    +
    + clocks {
    + 2d {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&gr2d_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_GR2D>;
    + power-domains = <&pd_core>;
    + };
    +
    + 3d {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&gr3d_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_GR3D>;
    + power-domains = <&pd_core>;
    + };
    +
    + dsi {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&dsi_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_DSI>;
    + power-domains = <&pd_core>;
    + };
    +
    + epp {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&epp_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_EPP>;
    + power-domains = <&pd_core>;
    + };
    +
    + hdmi {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&hdmi_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_HDMI>;
    + power-domains = <&pd_core>;
    + };
    +
    + host1x {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&host1x_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
    + power-domains = <&pd_core>;
    + };
    +
    + ide {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&ide_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_IDE>;
    + power-domains = <&pd_core>;
    + };
    +
    + mipi {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&mipi_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_MIPI>;
    + power-domains = <&pd_core>;
    + };
    +
    + mpe {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&mpe_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_MPE>;
    + power-domains = <&pd_core>;
    + };
    +
    + ndflash {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&ndflash_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
    + power-domains = <&pd_core>;
    + };
    +
    + nor {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&nor_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_NOR>;
    + power-domains = <&pd_core>;
    + };
    +
    + pex {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&pcie_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_PEX>;
    + power-domains = <&pd_core>;
    + };
    +
    + sdmmc1 {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
    + power-domains = <&pd_core>;
    + };
    +
    + sdmmc2 {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
    + power-domains = <&pd_core>;
    + };
    +
    + sdmmc3 {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
    + power-domains = <&pd_core>;
    + };
    +
    + sdmmc4 {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
    + power-domains = <&pd_core>;
    + };
    +
    + sclk {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&sclk_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_SCLK>;
    + power-domains = <&pd_core>;
    + };
    +
    + tvo {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&tvo_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_TVO>;
    + power-domains = <&pd_core>;
    + };
    +
    + usbd {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&usbd_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_USBD>;
    + power-domains = <&pd_core>;
    + };
    +
    + usb2 {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&usb2_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_USB2>;
    + power-domains = <&pd_core>;
    + };
    +
    + usb3 {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&usb3_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_USB3>;
    + power-domains = <&pd_core>;
    + };
    +
    + vde {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&vde_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_VDE>;
    + power-domains = <&pd_core>;
    + };
    +
    + vi {
    + compatible = "nvidia,tegra20-clock";
    + operating-points-v2 = <&vi_dvfs_opp_table>;
    + clocks = <&tegra_car TEGRA20_CLK_VI>;
    + power-domains = <&pd_core>;
    + };
    + };
    };

    flow-controller@60007000 {
    @@ -319,6 +496,8 @@ vde@6001a000 {
    clocks = <&tegra_car TEGRA20_CLK_VDE>;
    reset-names = "vde", "mc";
    resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
    + operating-points-v2 = <&vde_dvfs_opp_table>;
    + power-domains = <&pd_vde>;
    };

    apbmisc@70000800 {
    @@ -643,6 +822,40 @@ tegra_pmc: pmc@7000e400 {
    clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
    clock-names = "pclk", "clk32k_in";
    #clock-cells = <1>;
    +
    + powergates {
    + pd_3d: 3d {
    + clocks = <&tegra_car TEGRA20_CLK_GR3D>;
    + resets = <&tegra_car TEGRA20_CLK_GR3D>;
    + power-domains = <&pd_core>;
    + #power-domain-cells = <0>;
    + };
    +
    + pd_venc: venc {
    + clocks = <&tegra_car TEGRA20_CLK_ISP>,
    + <&tegra_car TEGRA20_CLK_VI>,
    + <&tegra_car TEGRA20_CLK_CSI>;
    + resets = <&tegra_car TEGRA20_CLK_ISP>,
    + <&tegra_car 20 /* VI */>,
    + <&tegra_car TEGRA20_CLK_CSI>;
    + power-domains = <&pd_core>;
    + #power-domain-cells = <0>;
    + };
    +
    + pd_vde: vdec {
    + clocks = <&tegra_car TEGRA20_CLK_VDE>;
    + resets = <&tegra_car TEGRA20_CLK_VDE>;
    + power-domains = <&pd_core>;
    + #power-domain-cells = <0>;
    + };
    +
    + pd_mpe: mpe {
    + clocks = <&tegra_car TEGRA20_CLK_MPE>;
    + resets = <&tegra_car TEGRA20_CLK_MPE>;
    + power-domains = <&pd_core>;
    + #power-domain-cells = <0>;
    + };
    + };
    };

    mc: memory-controller@7000f000 {
    @@ -662,6 +875,7 @@ emc: memory-controller@7000f400 {
    reg = <0x7000f400 0x400>;
    interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&tegra_car TEGRA20_CLK_EMC>;
    + power-domains = <&pd_core>;
    #address-cells = <1>;
    #size-cells = <0>;
    #interconnect-cells = <0>;
    @@ -887,6 +1101,12 @@ mmc@c8000600 {
    status = "disabled";
    };

    + pd_core: core-domain {
    + compatible = "nvidia,tegra20-core-domain";
    + operating-points-v2 = <&core_opp_table>;
    + #power-domain-cells = <0>;
    + };
    +
    cpus {
    #address-cells = <1>;
    #size-cells = <0>;
    --
    2.29.2
    \
     
     \ /
      Last update: 2020-12-17 19:40    [W:5.978 / U:0.016 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site