Messages in this thread | | | Subject | Re: [PATCH] MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too | From | Zhou Yanjie <> | Date | Mon, 14 Dec 2020 03:12:23 +0800 |
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Hi Paul,
On 2020/12/12 上午8:03, Paul Cercueil wrote: > The JZ4760 has the HPTLB as well, but has a XBurst CPU with a D0 CPUID. > > Disable the HPTLB for all XBurst CPUs with a D0 CPUID. In the case where > there is no HPTLB (e.g. for older SoCs), this won't have any side > effect. > > Fixes: b02efeb05699 ("MIPS: Ingenic: Disable abandoned HPTLB function.") > Cc: <stable@vger.kernel.org> # 5.4 > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > --- > arch/mips/kernel/cpu-probe.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index e6853697a056..31cb9199197c 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -1830,16 +1830,17 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) > */ > case PRID_COMP_INGENIC_D0: > c->isa_level &= ~MIPS_CPU_ISA_M32R2; > - break; > + fallthrough; > > /* > * The config0 register in the XBurst CPUs with a processor ID of > - * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this > - * mode is not compatible with the MIPS standard, it will cause > - * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S) > - * when starting the init process. After chip reset, the default > - * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
I just noticed that I mistakenly wrote a capital 'W' in the original version.
with that fixed:
Reviewed-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
BTW: Are you planning to add support for JZ4760 recently? I am currently writing the CGU driver for JZ4775 and X2000. If you plan to add support for JZ4760, I can also write the CGU driver for JZ4760 by the way.
Thanks and best regards!
> - * switch back to VTLB mode to prevent getting stuck. > + * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned > + * huge page tlb mode, this mode is not compatible with the MIPS > + * standard, it will cause tlbmiss and into an infinite loop > + * (line 21 in the tlb-funcs.S) when starting the init process. > + * After chip reset, the default is HPTLB mode, Write 0xa9000000 > + * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent > + * getting stuck. > */ > case PRID_COMP_INGENIC_D1: > write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
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