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SubjectRe: [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register
On Wed, Jul 24, 2019 at 09:11:01AM -0400, Liang, Kan wrote:
>
>
> On 7/24/2019 4:29 AM, Yunying Sun wrote:
> > From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
> > counting hardware generated prefetches of L3 cache. But current bitmasks
> > in driver takes bit 13 as invalid. Here to fix it.
> >
> > Before:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> > Performance counter stats for 'sleep 3':
> > <not supported> cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> >
> > After:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> > Performance counter stats for 'sleep 3':
> > 9,293 cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> >
> > Signed-off-by: Yunying Sun <yunying.sun@intel.com>
>
> Thanks Yunying.
>
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks!

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