Messages in this thread | | | Date | Fri, 08 Dec 2006 12:18:52 +1100 | From | Nick Piggin <> | Subject | Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch doesn't support it |
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Russell King wrote: > On Thu, Dec 07, 2006 at 08:31:08PM +1100, Nick Piggin wrote:
>>>Implementing ll/sc based accessor macros allows both ll/sc _and_ cmpxchg >>>architectures to produce optimal code. >>> >>>Implementing an cmpxchg based accessor macro allows cmpxchg architectures >>>to produce optimal code and ll/sc non-optimal code. >>> >>>See my point? >> >>Wrong. Your ll/sc implementation with cmpxchg is buggy. The cmpxchg >>load_locked is not locked at all, > > > Intentional - cmpxchg architectures don't generally have a load locked.
Exactly, so it is wrong -- you can't implement that behaviour with load + cmpxchg.
>>and there can be interleaving writes >>between the load and cmpxchg which do not cause the store_conditional >>to fail. > > > In which case the cmpxchg fails and we do the atomic operation again, > in exactly the same way that we do the operation again if the 'sc' > fails in the ll/sc case.
Not if cmpxchg sees the same value, it won't fail, regardless of how many writes have hit that memory address.
> I do not see any problem.
This was not the big problem -- as I said, if this was the only problem we could opt for a "watered down" version that doesn't actually load locked [the ll/sc interface would be much cooler than cmpxchg, IMO :)]
The main problem is the restrictions between the ll and sc. This is why I implemented atomic_cmpxchg rather than atomic_ll/sc. However I agree that in critical code, a higher level API should be used instead (eg. see atomic_add_unless, which can be implemented optimally on RISCs).
Nick
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