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SubjectRe: [PATCH v2 03/12] dt-bindings: phy: add rockchip usbdp combo phy document
On Tue, Feb 13, 2024 at 05:32:37PM +0100, Sebastian Reichel wrote:
> + rockchip,dp-lane-mux:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 2
> + maxItems: 4
> + description:
> + An array of physical Type-C lanes indexes. Position of an entry
> + determines the DisplayPort (DP) lane index, while the value of an entry
> + indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
> + e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
> + 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
> + lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
> + <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
> + phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3.

> If
> + DP lane map by DisplayPort Alt mode, this property is not need.

You missed one of the nits I pointed out on the previous version:
"If DP lanes are mapped by" "not needed."

Otherwise, I think this looks okay to me..
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.
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