lkml.org 
[lkml]   [2022]   [Sep]   [19]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH net-next v2 5/5] net: mediatek: sgmii: refactor power cycling into mtk_pcs_config()
    Date
    Both code paths (autonegotiated and force mode) are power cycling
    the phy. Move power cycling code to the caller to remove code
    duplicity.

    Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
    ---
    drivers/net/ethernet/mediatek/mtk_sgmii.c | 45 ++++++++---------------
    1 file changed, 15 insertions(+), 30 deletions(-)

    diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
    index 4c8e8c7b1d32..50f605208295 100644
    --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
    +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
    @@ -25,9 +25,6 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface
    {
    unsigned int val;

    - /* PHYA power down */
    - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
    -
    /* Set SGMII phy speed */
    regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
    val &= ~RG_PHY_SPEED_MASK;
    @@ -48,18 +45,6 @@ static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface
    val |= SGMII_AN_RESTART | SGMII_AN_ENABLE;
    regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);

    - /* Release PHYA power down state
    - * Only removing bit SGMII_PHYA_PWD isn't enough.
    - * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
    - * prevents SGMII from working. The SGMII still shows link but no traffic
    - * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
    - * taken from a good working state of the SGMII interface.
    - * Unknown how much the QPHY needs but it is racy without a sleep.
    - * Tested on mt7622 & mt7986.
    - */
    - usleep_range(50, 100);
    - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
    -
    return 0;

    }
    @@ -72,9 +57,6 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
    {
    unsigned int val;

    - /* PHYA power down */
    - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
    -
    regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
    val &= ~RG_PHY_SPEED_MASK;
    if (interface == PHY_INTERFACE_MODE_2500BASEX)
    @@ -92,18 +74,6 @@ static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
    val |= SGMII_SPEED_1000;
    regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);

    - /* Release PHYA power down state
    - * Only removing bit SGMII_PHYA_PWD isn't enough.
    - * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
    - * prevents SGMII from working. The SGMII still shows link but no traffic
    - * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
    - * taken from a good working state of the SGMII interface.
    - * Unknown how much the QPHY needs but it is racy without a sleep.
    - * Tested on mt7622 & mt7986.
    - */
    - usleep_range(50, 100);
    - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
    -
    return 0;
    }

    @@ -115,12 +85,27 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
    struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
    int err = 0;

    + /* PHYA power down */
    + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
    +
    /* Setup SGMIISYS with the determined property */
    if (interface != PHY_INTERFACE_MODE_SGMII)
    err = mtk_pcs_setup_mode_force(mpcs, interface);
    else if (phylink_autoneg_inband(mode))
    err = mtk_pcs_setup_mode_an(mpcs, interface);

    + /* Release PHYA power down state
    + * Only removing bit SGMII_PHYA_PWD isn't enough.
    + * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
    + * prevents SGMII from working. The SGMII still shows link but no traffic
    + * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
    + * taken from a good working state of the SGMII interface.
    + * Unknown how much the QPHY needs but it is racy without a sleep.
    + * Tested on mt7622 & mt7986.
    + */
    + usleep_range(50, 100);
    + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
    +
    return err;
    }

    --
    2.37.3
    \
     
     \ /
      Last update: 2022-09-19 10:53    [W:3.242 / U:0.096 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site